2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be
connected between the ZQ pin and ground. A single resistor can be used for each device
or one resistor can be shared between multiple devices if the ZQ calibration timings for
each device do not overlap. The total capacitive loading on the ZQ pin must be limited
(see the Input/Output Capacitance table).
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS# is HIGH at
the rising edge of clock. A NOP command must be driven in the clock cycle following
power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE opera-
tions are in progress. CKE can go LOW while any other operations such as ACTIVATE,
PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down I DD
specification will not be applied until such operations are complete.
If power-down occurs when all banks are idle, this mode is referred to as idle power-
down; if power-down occurs when there is a row active in any bank, this mode is refer-
red to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, and
CKE. In power-down mode, CKE must be held LOW; all other input signals are “Don’t
Care.” CKE LOW must be maintained until t CKE is satisfied. V REFCA must be maintained
at a valid level during power-down.
V DDQ can be turned off during power-down. If V DDQ is turned off, V REFDQ must also be
turned off. Prior to exiting power-down, both V DDQ and V REFDQ must be within their re-
spective minimum/maximum operating ranges (see AC and DC Operating Conditions).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is only limited by the refresh requirements outlined in REFRESH
Command.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS# HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until t CKE is satisfied. A valid, executable command can be
applied with power-down exit latency t XP after CKE goes HIGH. Power-down exit laten-
cy is defined in the AC Timing section.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
94
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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